Clocking
Table 62. CSB Frequency Options for Agent Mode
Input Clock Frequency (MHz)2
CFG_CLKIN_DIV
at Reset1
csb_clk :
SPMF
16.67
25
33.33
66.67
Input Clock Ratio2
csb_clk Frequency (MHz)
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
High
High
High
High
High
High
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0010
0011
0100
0101
0110
0111
1000
2 : 1
3 : 1
133
200
266
333
100
4 : 1
100
125
150
175
200
225
250
275
300
325
133
166
200
233
266
300
333
5 : 1
6 : 1
100
7 : 1
116
133
150
166
183
200
216
8 : 1
9 : 1
10 : 1
11 : 1
12 : 1
13 : 1
14 : 1
15 : 1
16 : 1
4 : 1
233
250
266
100
150
200
250
300
133
200
266
333
266
6 : 1
100
133
166
200
233
266
8 : 1
10 : 1
12 : 1
14 : 1
16 : 1
1
2
CFG_CLKIN_DIV doubles csb_clk if set high.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
DDR2 memory may be used at 133 MHz provided that the memory components are specified for operation at this frequency.
19.2 Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 63 shows the encodings for RCWL[COREPLL]. COREPLL values that are
not listed in Table 63 should be considered as reserved.
NOTE
Core VCO frequency = core frequency × VCO divider
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
81
FREESCALE [ Freescale ]
