Clocking
Addressed by This Document,” for part ordering details and contact your Freescale Sales Representative
or authorized distributor for more information.
Table 58. Operating Frequencies for TBGA
Characteristic1
e300 core frequency (core_clk)
400 MHz
266–400
533 MHz
266–533
667 MHz
266–667
Unit
MHz
Coherent system bus frequency (csb_clk)
DDR1 memory bus frequency (MCK)2
DDR2 memory bus frequency (MCK)3
Local bus frequency (LCLKn)4
100–266
100–133
100–133
16.67–133
25–66
100–333
100–133
100–200
16.67–133
25–66
100–333
100–166.67
100–200
16.67–133
25–66
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PCI input frequency (CLKIN or PCI_CLK)
Security core maximum internal operating frequency
133
133
166
USB_DR, USB_MPH maximum internal operating
frequency
133
133
166
1
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK,
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal
operating frequency of the Security core and USB modules does not exceed the respective values listed in this table.
The DDR data rate is 2x the DDR memory bus frequency.
The DDR data rate is 2x the DDR memory bus frequency.
The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x
the csb_clk frequency (depending on RCWL[LBIUCM]).
2
3
4
Table 59 provides the operating frequencies for the MPC8347EA PBGA under recommended operating
conditions.
Table 59. Operating Frequencies for PBGA
Parameter1
266 MHz
333 MHz
400 MHz
Unit
MHz
e300 core frequency (core_clk)
200–266
200–333
100–266
100–133
100–133
16.67–133
25–66
200–400
Coherent system bus frequency (csb_clk)
DDR1 memory bus frequency (MCK)2
DDR2 memory bus frequency (MCK)3
Local bus frequency (LCLKn)4
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PCI input frequency (CLKIN or PCI_CLK)
Security core maximum internal operating frequency
133
USB_DR, USB_MPH maximum internal operating
frequency
133
1
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK,
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal
operating frequency of the Security core and USB modules does not exceed the respective values listed in this table.
The DDR data rate is 2× the DDR memory bus frequency.
2
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
78
Freescale Semiconductor
FREESCALE [ Freescale ]
