DUART
Figure 7 shows the DDR SDRAM output timing diagram.
MCK[n]
MCK[n]
tMCK
tDDKHAS,tDDKHCS
tDDKHAX,tDDKHCX
ADDR/CMD/MODT
Write A0
tDDKHMP
NOOP
tDDKHMH
MDQS[n]
MDQ[x]
tDDKHME
tDDKHDS
tDDKLDS
D0
D1
tDDKLDX
tDDKHDX
Figure 7. DDR SDRAM Output Timing Diagram
Figure 8 provides the AC test load for the DDR bus.
GVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 8. DDR AC Test Load
7 DUART
This section describes the DC and AC electrical specifications for the DUART interface of the
MPC8347EA.
7.1
DUART DC Electrical Characteristics
Table 21 provides the DC electrical characteristics for the DUART interface of the MPC8347EA.
Table 21. DUART DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
Low-level input voltage
VIH
VIL
IIN
2
OVDD + 0.3
V
V
–0.3
—
0.8
5
Input current (0.8 V ≤ VIN ≤ 2 V)
μA
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
22
FREESCALE [ Freescale ]
