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MPC8347ECVVAGDB 参数 Datasheet PDF下载

MPC8347ECVVAGDB图片预览
型号: MPC8347ECVVAGDB
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8347EA的PowerQUICC II Pro整合型主机处理器的硬件规格 [MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications]
分类和应用: 外围集成电路PC时钟
文件页数/大小: 99 页 / 727 K
品牌: FREESCALE [ Freescale ]
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Ethernet: Three-Speed Ethernet, MII Management  
Table 26. GMII Receive AC Timing Specifications (continued)  
At recommended operating conditions with LVDD/OVDD of 3.3 V 10%.  
Parameter/Condition  
Symbol1  
Min  
Typ  
Max  
Unit  
RX_CLK clock rise (20%–80%)  
RX_CLK clock fall time (80%–20%)  
Note:  
tGRXR  
tGRXF  
1.0  
1.0  
ns  
ns  
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs  
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII receive timing  
(GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K) going  
to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the time data input  
signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. In general, the clock  
reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of tGRX  
represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:  
R (rise) or F (fall).  
Figure 10 shows the GMII receive AC timing diagram.  
G
tGRX  
tGRXR  
RX_CLK  
tGRXF  
tGRXH  
RXD[7:0]  
RX_DV  
RX_ER  
tGRDXKH  
tGRDVKH  
Figure 10. GMII Receive AC Timing Diagram  
8.2.2  
MII AC Timing Specifications  
This section describes the MII transmit and receive AC timing specifications.  
8.2.2.1  
MII Transmit AC Timing Specifications  
Table 27 provides the MII transmit AC timing specifications.  
Table 27. MII Transmit AC Timing Specifications  
At recommended operating conditions with LVDD/OVDD of 3.3 V 10%.  
Parameter/Condition  
Symbol1  
Min  
Typ  
Max  
Unit  
TX_CLK clock period 10 Mbps  
TX_CLK clock period 100 Mbps  
TX_CLK duty cycle  
tMTX  
tMTX  
tMTXH/ MTX  
tMTKHDX  
35  
1
400  
40  
5
65  
15  
ns  
ns  
%
t
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay  
ns  
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12  
Freescale Semiconductor  
26