Ethernet: Three-Speed Ethernet, MII Management
8.2.1.1
GMII Transmit AC Timing Specifications
Table 25 provides the GMII transmit AC timing specifications.
Table 25. GMII Transmit AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V 10%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
GTX_CLK clock period
tGTX
GTXH/tGTX
tGTKHDX
tGTXR
—
43.75
0.5
8.0
—
—
—
—
—
56.25
5.0
ns
%
GTX_CLK duty cycle
t
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
GTX_CLK clock rise time (20%–80%)
GTX_CLK clock fall time (80%–20%)
Notes:
ns
ns
ns
—
1.0
tGTXF
—
1.0
1. The symbols for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and
(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing (GT)
t
with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching the
valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock
reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. In general,
the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript
of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
Figure 9 shows the GMII transmit AC timing diagram.
t
t
GTXR
GTX
GTX_CLK
t
t
GTXF
GTXH
TXD[7:0]
TX_EN
TX_ER
t
GTKHDX
Figure 9. GMII Transmit AC Timing Diagram
8.2.1.2
GMII Receive AC Timing Specifications
Table 26 provides the GMII receive AC timing specifications.
Table 26. GMII Receive AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V 10%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
RX_CLK clock period
tGRX
—
40
8.0
—
—
—
—
60
—
—
ns
%
RX_CLK duty cycle
tGRXH/tGRX
tGRDVKH
tGRDXKH
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
2.0
0.5
ns
ns
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
25
FREESCALE [ Freescale ]
