Electrical Characteristics
Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8347EA for the
3.3-V signals, respectively.
11 ns
(Min)
+7.1 V
Overvoltage
Waveform
7.1 V p-to-p
(Min)
0 V
4 ns
(Max)
4 ns
(Max)
62.5 ns
+3.6 V
Undervoltage
Waveform
7.1 V p-to-p
(Min)
–3.5 V
Figure 3. Maximum AC Waveforms on PCI Interface for 3.3-V Signaling
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Table 3. Output Drive Capability
Output Impedance
Supply
Voltage
Driver Type
(Ω)
Local bus interface utilities signals
PCI signals (not including PCI output clocks)
PCI output clocks (including PCI_SYNC_OUT)
DDR signal
40
25
40
18
OVDD = 3.3 V
GVDD = 2.5 V
GVDD = 1.8 V
DDR2 signal
18
36 (half-strength mode)
TSEC/10/100 signals
DUART, system control, I2C, JTAG, USB
40
40
40
LVDD = 2.5/3.3 V
OVDD = 3.3 V
GPIO signals
OVDD = 3.3 V,
LVDD = 2.5/3.3 V
2.2
Power Sequencing
This section details the power sequencing considerations for the MPC8347EA.
2.2.1
Power-Up Sequencing
MPC8347EAdoes not require the core supply voltage (V and AV ) and I/O supply voltages (GV ,
DD
DD
DD
LV , and OV ) to be applied in any particular order. During the power ramp up, before the power
DD
DD
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
9
FREESCALE [ Freescale ]
