Communication interfaces
6.8.5 I2S/SAI Switching Specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
All timing shown is also with respect to input signal transitions of 3 ns and a 50 pF
maximum load.
Table 35. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
40
3.6
V
I2S_MCLK cycle time1
S1
S2
S3
ns
I2S_MCLK pulse width high/low
I2S_TX_BCLK cycle time (output)1
I2S_RX_BCLK cycle time (output)1
I2S_TX_BCLK pulse width high/low
45%
80
55%
—
MCLK period
ns
160
—
S4
S5
45%
—
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
15
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
25
S10
S11
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid2
0
—
ns
ns
—
21
1. This parameter is limited in VLPx modes.
2. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
MCF51JU128 Data Sheet, Rev. 4, 01/2012.
Freescale Semiconductor, Inc.
51
FREESCALE [ Freescale ]
