Communication interfaces
Table 32. USB VREG electrical specifications
(continued)
Typ.1
Symbol Description
Min.
Max.
Unit
Notes
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
3
3.3
2.8
—
3.6
3.6
3.6
V
V
V
• Standby mode
2.1
2.1
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2
COUT
ESR
External output capacitor
1.76
1
2.2
—
8.16
100
μF
External output capacitor equivalent series
resistance
mΩ
ILIM
Short circuit current
—
290
—
mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad
.
6.8.4 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. See the SPI chapter of the
chip's Reference Manual for information about the modified transfer formats used for
communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 70% VDD, unless noted, as well as
input signal transitions of 3 ns and a 50 pF maximum load on all SPI pins. All timing
assumes slew rate control is disabled and high drive strength is enabled for SPI output
pins.
Table 33. SPI master mode timing
Num.
Symbol Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
fBUS/2048
fBUS/2
Hz
fBUS is the
bus clock
as defined
in Table 8.
2
tSPSCK
SPSCK period
2 x tBUS
2048 x
tBUS
ns
tBUS = 1/
fBUS
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tBUS - 30
1024 x
tBUS
Table continues on the next page...
MCF51JU128 Data Sheet, Rev. 4, 01/2012.
Freescale Semiconductor, Inc.
47
FREESCALE [ Freescale ]
