Communication interfaces
Table 33. SPI master mode timing (continued)
Num.
Symbol Description
Min.
Max.
Unit
Comment
6
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
21
—
ns
—
7
8
0
—
0
—
25
ns
ns
ns
ns
—
—
—
—
tv
9
tHO
tRI
—
10
—
tBUS - 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
5
=
(CPOL 0)
(OUTPUT)
5
SPSCK
(CPOL 1)
=
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
LSB OUT
MSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 14. SPI master mode timing (CPHA=0)
MCF51JU128 Data Sheet, Rev. 4, 01/2012.
48
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
