Communication interfaces
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL 0)
=
(OUTPUT)
5
5
SPSCK
(CPOL 1)
=
(OUTPUT)
6
7
MISO
(INPUT)
2
MSB IN
BIT 6 . . . 1
LSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
MASTER MSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 15. SPI master mode timing (CPHA=1)
Table 34. SPI slave mode timing
Num.
Symbol Description
Min.
Max.
fBUS/4
Unit
Comment
1
fop
Frequency of operation
0
Hz
fBUS is the
bus clock
as defined
in Table 8.
2
tSPSCK
SPSCK period
4 x tBUS
—
ns
tBUS = 1/
fBUS
3
4
5
6
7
8
tLead
tLag
Enable lead time
Enable lag time
1
—
—
tBUS
tBUS
ns
—
—
—
—
—
1
tBUS - 30
19.5
0
tWSPSCK Clock (SPSCK) high or low time
—
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
—
ns
—
ns
—
tBUS
ns
Time to
data active
from high-
impedanc
e state
9
tdis
Slave MISO disable time
—
tBUS
ns
Hold time
to high-
impedanc
e state
10
11
tv
Data valid (after SPSCK edge)
Data hold time (outputs)
—
0
27
—
ns
ns
—
—
tHO
Table continues on the next page...
MCF51JU128 Data Sheet, Rev. 4, 01/2012.
Freescale Semiconductor, Inc.
49
FREESCALE [ Freescale ]
