Communication interfaces
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 18. I2S/SAI timing — master modes
Table 36. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
80
3.6
—
V
S11
I2S_RX_BCLK cycle time (input)
I2S_TX_BCLK cycle time (input)
ns
160
—
S12
S13
S14
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
10
2
55%
MCLK period
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
29
—
—
—
21
ns
ns
ns
ns
ns
10
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
MCF51JU128 Data Sheet, Rev. 4, 01/2012.
52
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
