Pinout
8 Pinout
8.1 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Mux Control module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
• On PTB0, EZP_MS_b is active only during reset. Refer to
the detailed boot description.
• PTC1 is open drain.
64-
pin
48-
pin
44-
pin
32-
pin
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
1
2
3
4
5
—
—
—
—
1
—
—
—
—
—
—
—
—
—
—
VDD
VDD
VSS
VSS
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
PTC6
UART0_TX
I2C0_SCL
RGPIO6
RGPIO7
RGPIO8
SPI1_MOSI FBa_AD11
SPI1_MISO FBa_AD12
SPI1_SCLK FBa_AD13
PTC7
PTD0
UART0_RX I2C0_SDA
UART0_CT
S_b
I2C1_SDA
I2S0_MCLK
/
I2S0_CLKIN
6
7
2
3
—
1
—
1
Disabled
Disabled
Disabled
Disabled
PTD1
PTA0
UART0_RT
S_b
I2C1_SCL
I2C2_SCL
I2C2_SDA
RGPIO9
SPI1_SS
SPI0_SS
FBa_AD14
FBa_AD15
FBa_AD16
I2S0_RX_B
CLK
FTM1_CH0
I2S0_RX_F
S
8
9
4
5
6
2
3
4
2
3
4
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
PTA1
PTA2
PTA3
FTM1_CH1
FTM1_CH2
FTM1_CH3
I2S0_RXD
UART1_TX
UART1_RX
SPI1_SS
10
SPI1_SCLK
I2S0_TX_B
CLK
EZP_CLK
EZP_DI
11
12
7
8
5
6
5
6
ADC0_SE2
ADC0_SE3
ADC0_SE2
ADC0_SE3
PTA4
PTA5
UART1_CT
S_b
I2C2_SCL
I2C2_SDA
FTM1_CH4
FTM1_CH5
SPI1_MISO
I2S0_TX_F
S
UART1_RT
S_b
SPI1_MOSI CLKOUT
I2S0_TXD
EZP_DO
13
14
15
16
17
18
19
20
21
9
7
7
VDDA
VDDA
10
11
12
13
14
15
16
17
8
—
—
—
8
VREFH
VREFH
9
VREF_OUT VREF_OUT
10
11
12
13
14
15
VREFL
VSSA
VREFL
VSSA
9
DAC0_OUT DAC0_OUT
10
11
12
VREGIN
VOUT33
USB0_DM
VREGIN
VOUT33
USB0_DM
MCF51JU128 Data Sheet, Rev. 4, 01/2012.
Freescale Semiconductor, Inc.
55
FREESCALE [ Freescale ]
