Port Integration Module (S12PPIMV1)
2.3.60 Port AD Data Direction Register (DDR1AD)
Address 0x0273
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
W
DDR1AD7
DDR1AD6
DDR1AD5
DDR1AD4
DDR1AD3
DDR1AD2
DDR1AD1
DDR1AD0
Reset
0
0
0
0
0
0
0
0
Figure 2-58. Port AD Data Direction Register (DDR1AD)
1. Read: Anytime
Write: Anytime
Table 2-54. DDR1AD Register Field Descriptions
Description
Field
7-0
Port AD data direction—
DDR1AD This bit determines whether the associated pin is an input or output.
To use the digital input function the ATD Digital Input Enable Register (ATDDIEN) has to be set to logic level “1”.
1 Associated pin is configured as output
0 Associated pin is configured as input
2.3.61 Port AD Reduced Drive Register (RDR0AD)
Address 0x0274
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
0
RDR0AD1
RDR0AD0
Reset
0
0
0
0
0
0
0
0
Figure 2-59. Port AD Reduced Drive Register (RDR0AD)
1. Read: Anytime
Write: Anytime
Table 2-55. RDR0AD Register Field Descriptions
Description
Field
1-0
Port AD reduced drive—Select reduced drive for output pin
RDR0AD This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
S12P-Family Reference Manual, Rev. 1.13
98
Freescale Semiconductor
FREESCALE [ Freescale ]
