Chapter 2 Port Integration Module (S12PPIMV1)
Revision History
Rev. No.
(Item No.) (Submitted By)
Date
Sections
Affected
Substantial Change(s)
V01.00
V01.01
V01.02
19 Mar 2008
05 May 2008
12 Jan 2009
Initial version
Corrected mistakes in Port J register and field names
Corrected PERxAD register descriptions
Replaced VREG_API with API_EXTCLK
Minor corrections
2.1
Introduction
Overview
2.1.1
The S12P Family Port Integration Module establishes the interface between the peripheral modules and
the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and
multiplexing on shared pins.
This section covers:
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Port A and B used as general purpose I/O
Port E associated with the IRQ, XIRQ interrupt inputs
Port T associated with 1 timer module
Port S associated with 1 SCI module
Port M associated with 1 MSCAN and 1 SPI module
Port P connected to the PWM - inputs can be used as an external interrupt source
Port J used as general purpose I/O - inputs can be used as an external interrupt source
Port AD associated with one 10-channel ATD module
Most I/O pins can be configured by register bits to select data direction and drive strength, to enable and
select pull-up or pull-down devices.
NOTE
This section assumes the availability of all features (80-pin package option).
Some functions are not available on lower pin count package options. Refer
to the pin-out summary section.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
49
FREESCALE [ Freescale ]
