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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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Device Overview MC9S12P-Family  
1.12 COP Configuration  
The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register at address 0x003C are  
loaded from the Flash register FOPT. See Table 1-13 and Table 1-14 for coding. The FOPT register is  
loaded from the Flash configuration field byte at global address 0x3_FF0E during the reset sequence.  
Table 1-13. Initial COP Rate Configuration  
NV[2:0] in  
CR[2:0] in  
FOPT Register  
COPCTL Register  
000  
001  
010  
011  
100  
101  
110  
111  
111  
110  
101  
100  
011  
010  
001  
000  
Table 1-14. Initial WCOP Configuration  
NV[3] in  
WCOP in  
FOPT Register  
COPCTL Register  
1
0
0
1
1.13 ATD External Trigger Input Connection  
The ATD module includes external trigger inputs ETRIG0 and ETRIG1. The external trigger allows the  
user to synchronize ATD conversion to external trigger events. Table 1-15 shows the connection of the  
external trigger inputs.  
Table 1-15. ATD External Trigger Sources  
External Trigger  
Connectivity  
Input  
ETRIG0  
ETRIG1  
PWM channel 1  
PWM channel 3  
Consult the ATD section for information about the analog-to-digital converter module. References to  
freeze mode are equivalent to active BDM mode.  
S12P-Family Reference Manual, Rev. 1.13  
Freescale Semiconductor  
47