Device Overview MC9S12P-Family
Table 1-12. Interrupt Vector Locations (Sheet 2 of 3)
CCR
Wake up
from STOP from WAIT
Wakeup
Vector Address(1)
Interrupt Source
Local Enable
Mask
Vector base+ $F0
RTI timeout interrupt
I bit
CPMUINT (RTIE)
7.6 Interrupts
Vector base+ $EE
Vector base + $EC
Vector base+ $EA
Vector base+ $E8
Vector base+ $E6
Vector base+ $E4
Vector base + $E2
Vector base+ $E0
Vector base+ $DE
TIM timer channel 0
TIM timer channel 1
TIM timer channel 2
TIM timer channel 3
TIM timer channel 4
TIM timer channel 5
TIM timer channel 6
TIM timer channel 7
TIM timer overflow
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
TIE (C0I)
TIE (C1I)
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
TSRC2 (TOF)
PACTL (PAOVI)
PACTL (PAI)
SPICR1 (SPIE, SPTIE)
Vector base+ $DC
Vector base + $DA
Vector base + $D8
Vector base+ $D6
TIM Pulse accumulator A overflow
TIM Pulse accumulator input edge
SPI
SCI
SCICR2
(TIE, TCIE, RIE, ILIE)
Vector base + $D4
Vector base + $D2
Vector base + $D0
Vector base + $CE
Reserved
ATDCTL2 (ASCIE)
Reserved
ATD
I bit
I bit
Yes
Yes
Yes
Yes
Port J
PIEJ (PIEJ7-PIEJ6, PIEJ2-
PIEJ0)
Vector base + $CC
to
Reserved
Vector base + $CA
Vector base + $C8
Vector base + $C6
Oscillator status interrupt
PLL lock interrupt
I bit
I bit
CPMUINT (OSCIE)
CPMUINT (LOCKIE)
No
No
No
No
Vector base + $C4
to
Reserved
Vector base + $BC
Vector base + $BA
Vector base + $B8
Vector base + $B6
Vector base + $B4
Vector base + $B2
Vector base + $B0
FLASH error
FLASH command
CAN wake-up
CAN errors
I bit
I bit
I bit
I bit
I bit
I bit
FERCNFG (SFDIE, DFDIE)
FCNFG (CCIE)
No
No
No
Yes
CANRIER (WUPIE)
CANRIER (CSCIE, OVRIE)
CANRIER (RXFIE)
8.4.7 Interrupts
CAN receive
CAN transmit
CANTIER (TXEIE[2:0])
S12P-Family Reference Manual, Rev. 1.13
45
Freescale Semiconductor
FREESCALE [ Freescale ]
