Device Overview MC9S12P-Family
Vector Address(1)
Table 1-12. Interrupt Vector Locations (Sheet 3 of 3)
CCR
Wake up
from STOP from WAIT
Wakeup
Interrupt Source
Local Enable
Mask
Vector base + $AE
to
Reserved
Vector base + $90
Vector base + $8E
Port P interrupt
I bit
I bit
I bit
PIEP (PIEP7,PIEP5-PIEP0)
PWMSDN (PWMIE)
Yes
No
No
Yes
Yes
Yes
Vector base+ $8C
Vector base + $8A
Vector base + $88
PWM emergency shutdown
Low-voltage interrupt (LVI)
CPMUCTRL (LVIE)
Autonomous periodical interrupt
(API)
I bit
CPMUAPICTRL (APIE)
Yes
Yes
Vector base + $86
Vector base + $84
Vector base + $82
Vector base + $80
High temperature interrupt
ATD compare interrupt
I bit
I bit
CPMUHTCL (HTIE)
ATDCTL2 (ACMPIE)
Reserved
No
Yes
Yes
Yes
Spurious interrupt
—
None
-
-
1. 16 bits vector address based
1.11.3 Effects of Reset
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections
for register reset states.
On each reset, the Flash module executes a reset sequence to load Flash configuration registers.
1.11.3.1 Flash Configuration Reset Sequence Phase
On each reset, the Flash module will hold CPU activity while loading Flash module registers from the
Flash memory. If double faults are detected in the reset phase, Flash module protection and security may
be active on leaving reset. This is explained in more detail in the Flash module section 13.6 Initialization.
1.11.3.2 Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.11.3.3 I/O Pins
Refer to the PIM section for reset configurations of all peripheral module ports.
1.11.3.4 Memory
The RAM arrays are not initialized out of reset.
S12P-Family Reference Manual, Rev. 1.13
46
Freescale Semiconductor
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