Serial Peripheral Interface (S12SPIV5)
12.3.2.3 SPI Baud Rate Register (SPIBR)
Module Base +0x0002
7
6
5
4
3
2
1
0
R
W
0
0
SPPR2
SPPR1
SPPR0
SPR2
SPR1
SPR0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-5. SPI Baud Rate Register (SPIBR)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Table 12-6. SPIBR Field Descriptions
Field
Description
SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in Table 12-7. In master
6–4
SPPR[2:0] mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state.
2–0
SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in Table 12-7. In master mode,
SPR[2:0]
a change of these bits will abort a transmission in progress and force the SPI system into idle state.
The baud rate divisor equation is as follows:
(SPR + 1)
BaudRateDivisor = (SPPR + 1) • 2
Eqn. 12-1
Eqn. 12-2
The baud rate can be calculated with the following equation:
Baud Rate = BusClock / BaudRateDivisor
NOTE
For maximum allowed baud rates, please refer to the SPI Electrical
Specification in the Electricals chapter of this data sheet.
Table 12-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 1 of 3)
Baud Rate
SPPR2
SPPR1
SPPR0
SPR2
SPR1
SPR0
Baud Rate
Divisor
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
2
4
12.5 Mbit/s
6.25 Mbit/s
8
3.125 Mbit/s
1.5625 Mbit/s
781.25 kbit/s
390.63 kbit/s
195.31 kbit/s
97.66 kbit/s
6.25 Mbit/s
16
32
64
128
256
4
8
3.125 Mbit/s
1.5625 Mbit/s
781.25 kbit/s
16
32
S12P-Family Reference Manual, Rev. 1.13
406
Freescale Semiconductor
FREESCALE [ Freescale ]
