Serial Peripheral Interface (S12SPIV5)
12.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
12.3.2.1 SPI Control Register 1 (SPICR1)
Module Base +0x0000
7
6
5
4
3
2
1
0
R
W
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
Reset
0
0
0
0
0
1
0
0
Figure 12-3. SPI Control Register 1 (SPICR1)
Read: Anytime
Write: Anytime
Table 12-2. SPICR1 Field Descriptions
Description
Field
7
SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set.
SPIE
0 SPI interrupts disabled.
1 SPI interrupts enabled.
6
SPE
SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system
functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset.
0 SPI disabled (lower power consumption).
1 SPI enabled, port pins are dedicated to SPI functions.
5
SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set.
0 SPTEF interrupt disabled.
SPTIE
1 SPTEF interrupt enabled.
4
SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode.
Switching the SPI from master to slave or vice versa forces the SPI system into idle state.
0 SPI is in slave mode.
MSTR
1 SPI is in master mode.
3
SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI
modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a
transmission in progress and force the SPI system into idle state.
CPOL
0 Active-high clocks selected. In idle state SCK is low.
1 Active-low clocks selected. In idle state SCK is high.
2
SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will
abort a transmission in progress and force the SPI system into idle state.
CPHA
0 Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock.
1 Sampling of data occurs at even edges (2,4,6,...) of the SCK clock.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
403
FREESCALE [ Freescale ]
