Serial Peripheral Interface (S12SPIV5)
12.2.3 SS — Slave Select Pin
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when it is configured as a master and it is used as an input to receive the slave select
signal when the SPI is configured as slave.
12.2.4 SCK — Serial Clock Pin
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
12.3 Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the SPI.
12.3.1 Module Memory Map
The memory map for the SPI is given in Figure 12-2. The address listed for each register is the sum of a
base address and an address offset. The base address is defined at the SoC level and the address offset is
defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have
no effect.
Register
Name
Bit 7
SPIE
0
6
5
SPTIE
0
4
3
2
CPHA
0
1
Bit 0
0x0000
SPICR1
R
SPE
MSTR
CPOL
SSOE
LSBFE
W
0x0001
SPICR2
R
XFRW
MODFEN
BIDIROE
0
SPISWAI
SPC0
W
0x0002
SPIBR
R
0
SPPR2
0
SPPR1
SPTEF
SPPR0
MODF
SPR2
0
SPR1
0
SPR0
0
W
0x0003
SPISR
R
SPIF
0
W
0x0004
SPIDRH
R
R15
T15
R14
T14
R13
T13
R12
T12
R11
T11
R10
T10
R9
T9
R8
T8
W
0x0005
SPIDRL
R
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
W
0x0006
R
Reserved
W
0x0007
R
Reserved
W
= Unimplemented or Reserved
Figure 12-2. SPI Register Summary
S12P-Family Reference Manual, Rev. 1.13
402
Freescale Semiconductor
FREESCALE [ Freescale ]
