Serial Peripheral Interface (S12SPIV5)
Table 12-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 3 of 3)
Baud Rate
Divisor
SPPR2
SPPR1
SPPR0
SPR2
SPR1
SPR0
Baud Rate
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
896
1792
16
27.90 kbit/s
13.95 kbit/s
1.5625 Mbit/s
781.25 kbit/s
390.63 kbit/s
195.31 kbit/s
97.66 kbit/s
48.83 kbit/s
24.41 kbit/s
12.21 kbit/s
32
64
128
256
512
1024
2048
12.3.2.4 SPI Status Register (SPISR)
Module Base +0x0003
7
6
5
4
3
2
1
0
R
W
SPIF
0
SPTEF
MODF
0
0
0
0
Reset
0
0
1
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-6. SPI Status Register (SPISR)
Read: Anytime
Write: Has no effect
Table 12-8. SPISR Field Descriptions
Description
Field
7
SPIF
SPIF Interrupt Flag — This bit is set after received data has been transferred into the SPI data register. For
information about clearing SPIF Flag, please refer to Table 12-9.
0 Transfer not yet complete.
1 New data copied to SPIDR.
5
SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. For
information about clearing this bit and placing data into the transmit data register, please refer to Table 12-10.
0 SPI data register not empty.
SPTEF
1 SPI data register empty.
4
Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode
fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Section 12.3.2.2, “SPI Control Register 2 (SPICR2)”. The flag is cleared automatically by a read of the SPI status
register (with MODF set) followed by a write to the SPI control register 1.
0 Mode fault has not occurred.
MODF
1 Mode fault has occurred.
S12P-Family Reference Manual, Rev. 1.13
408
Freescale Semiconductor
FREESCALE [ Freescale ]
