Serial Peripheral Interface (S12SPIV5)
12.3.2.5 SPI Data Register (SPIDR = SPIDRH:SPIDRL)
Module Base +0x0004
7
6
5
4
3
2
1
0
R
W
R15
R14
R13
R12
R11
R10
R9
R8
T15
0
T14
0
T13
0
T12
0
T11
0
T10
0
T9
0
T8
0
Reset
Figure 12-7. SPI Data Register High (SPIDRH)
Module Base +0x0005
7
6
5
4
3
2
1
0
R
W
R7
T7
0
R6
R5
R4
R3
R2
R1
R0
T6
0
T5
0
T4
0
T3
0
T2
0
T1
0
T0
0
Reset
Figure 12-8. SPI Data Register Low (SPIDRL)
Read: Anytime; read data only valid when SPIF is set
Write: Anytime
The SPI data register is both the input and output register for SPI data. A write to this register
allows data to be queued and transmitted. For an SPI configured as a master, queued data is
transmitted immediately after the previous transmission has completed. The SPI transmitter empty
flag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new data.
Received data in the SPIDR is valid when SPIF is set.
If SPIF is cleared and data has been received, the received data is transferred from the receive shift
register to the SPIDR and SPIF is set.
If SPIF is set and not serviced, and a second data value has been received, the second received data
is kept as valid data in the receive shift register until the start of another transmission. The data in
the SPIDR does not change.
If SPIF is set and valid data is in the receive shift register, and SPIF is serviced before the start of
a third transmission, the data in the receive shift register is transferred into the SPIDR and SPIF
remains set (see Figure 12-9).
If SPIF is set and valid data is in the receive shift register, and SPIF is serviced after the start of a
third transmission, the data in the receive shift register has become invalid and is not transferred
into the SPIDR (see Figure 12-10).
S12P-Family Reference Manual, Rev. 1.13
410
Freescale Semiconductor
FREESCALE [ Freescale ]
