Serial Peripheral Interface (S12SPIV5)
Table 12-2. SPICR1 Field Descriptions (continued)
Field
Description
1
Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by
asserting the SSOE as shown in Table 12-3. In master mode, a change of this bit will abort a transmission in
progress and force the SPI system into idle state.
SSOE
0
LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and
writes of the data register always have the MSB in the highest bit position. In master mode, a change of this bit
will abort a transmission in progress and force the SPI system into idle state.
0 Data is transferred most significant bit first.
LSBFE
1 Data is transferred least significant bit first.
Table 12-3. SS Input / Output Selection
MODFEN
SSOE
Master Mode
Slave Mode
0
0
1
1
0
1
0
1
SS not used by SPI
SS not used by SPI
SS input
SS input
SS input
SS input
SS input with MODF feature
SS is slave select output
12.3.2.2 SPI Control Register 2 (SPICR2)
Module Base +0x0001
7
6
5
4
3
2
1
0
R
W
0
0
0
XFRW
MODFEN
BIDIROE
SPISWAI
0
SPC0
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-4. SPI Control Register 2 (SPICR2)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
S12P-Family Reference Manual, Rev. 1.13
404
Freescale Semiconductor
FREESCALE [ Freescale ]
