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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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S12 Clock, Reset and Power Management Unit (S12CPMU)  
7.3.2.6  
S12CPMU Clock Select Register (CPMUCLKS)  
This register controls S12CPMU clock selection.  
0x0039  
7
6
5
4
3
2
1
0
R
W
0
0
RTI  
OSCSEL  
COP  
OSCSEL  
PLLSEL  
PSTP  
PRE  
PCE  
Reset  
1
0
0
0
0
0
0
0
= Unimplemented or Reserved  
Figure 7-9. S12CPMU Clock Select Register (CPMUCLKS)  
Read: Anytime  
Write:  
1. Only possible when PROT=0 (CPMUPROT register).  
2. All bits anytime in Special Modes.  
3. PLLSEL, PSTP, PRE, PCE, RTIOSCSEL: Anytime in Normal Mode.  
4. COPOSCSEL: Anytime in normal mode until CPMUCOP write once has taken place.  
If COPOSCSEL was cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL=1  
or insufficient OSCCLK quality), then COPOSCSEL can be set once again.  
After writing CPMUCLKS register, it is strongly recommended to read  
back CPMUCLKS register to make sure that write of PLLSEL,  
RTIOSCSEL and COPOSCSEL was successful.  
Table 7-5. CPMUCLKS Descriptions  
Description  
Field  
7
PLL Select Bit  
PLLSEL  
This bit selects the PLLCLK as source of the System Clocks (Core Clock and Bus Clock).  
PLLSEL can only be set to 0, if UPOSC=1.  
UPOSC= 0 sets the PLLSEL bit.  
Entering Full Stop Mode sets the PLLSEL bit.  
0 System clocks are derived from OSCCLK if oscillator is up (UPOSC=1, fbus = fosc / 2.  
1 System clocks are derived from PLLCLK, fbus = fPLL / 2.  
6
Pseudo Stop Bit  
PSTP  
This bit controls the functionality of the oscillator during Stop Mode.  
0 Oscillator is disabled in Stop Mode (Full Stop Mode).  
1 Oscillator continues to run in Stop Mode (Pseudo Stop Mode), option to run RTI and COP.  
Note: Pseudo Stop Mode allows for faster STOP recovery and reduces the mechanical stress and aging of the  
resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption.  
Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop  
Mode with OSCE bit is already 1) the software must wait for a minimum time equivalent to the startup-time  
of the external oscillator tUPOSC before entering Pseudo Stop Mode.  
S12P-Family Reference Manual, Rev. 1.13  
Freescale Semiconductor  
211  
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