S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2.8
S12CPMU RTI Control Register (CPMURTI)
This register selects the time-out period for the Real Time Interrupt.
The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL
bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode) and RTIOSCSEL=1 the RTI continues to run, else
the RTI counter halts in Stop Mode.
0x003B
7
6
5
4
3
2
1
0
R
W
RTDEC
RTR6
RTR5
RTR4
RTR3
RTR2
RTR1
RTR0
Reset
0
0
0
0
0
0
0
0
Figure 7-11. S12CPMU RTI Control Register (CPMURTI)
Read: Anytime
Write: Anytime
NOTE
A write to this register starts the RTI time-out period. A change of the
RTIOSCSEL bit (writing a different value or loosing UPOSC status)
re-starts the RTI time-out period.
Table 7-8. CPMURTI Field Descriptions
Description
Field
7
Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
0 Binary based divider value. See Table 7-9
RTDEC
1 Decimal based divider value. See Table 7-10
6–4
Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See Table 7-9
RTR[6:4]
and Table 7-10.
3–0
RTR[3:0]
Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional granularity.Table 7-9 and Table 7-10 show all possible divide values selectable by the
CPMURTI register.
S12P-Family Reference Manual, Rev. 1.13
214
Freescale Semiconductor
FREESCALE [ Freescale ]
