S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2.5
S12CPMU Interrupt Enable Register (CPMUINT)
This register enables S12CPMU interrupt requests.
0x0038
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
RTIE
LOCKIE
OSCIE
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-8. S12CPMU Interrupt Enable Register (CPMUINT)
Read: Anytime
Write: Anytime
Table 7-4. CRGINT Field Descriptions
Description
Field
7
Real Time Interrupt Enable Bit
0 Interrupt requests from RTI are disabled.
RTIE
1 Interrupt will be requested whenever RTIF is set.
4
PLL Lock Interrupt Enable Bit
LOCKIE
0 PLL LOCK interrupt requests are disabled.
1 Interrupt will be requested whenever LOCKIF is set.
1
Oscillator Corrupt Interrupt Enable Bit
OSCIE
0 Oscillator Corrupt interrupt requests are disabled.
1 Interrupt will be requested whenever OSCIF is set.
S12P-Family Reference Manual, Rev. 1.13
210
Freescale Semiconductor
FREESCALE [ Freescale ]
