S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2.3
S12CPMU Post Divider Register (CPMUPOSTDIV)
The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK.
0x0036
7
6
5
4
3
2
1
0
R
W
0
0
0
POSTDIV[4:0]
Reset
0
0
0
0
0
0
1
1
= Unimplemented or Reserved
Figure 7-6. S12CPMU Post Divider Register (CPMUPOSTDIV)
Read: Anytime
Write: If PLLSEL=1 write anytime, else write has no effect.
f
VCO
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
If PLL is selected (PLLSEL=1)
f
f
=
=
----------------------------------------
PLL
PLL
(POSTDIV + 1)
f
VCO
---------------
4
f
PLL
------------
2
f
=
bus
7.3.2.4
S12CPMU Flags Register (CPMUFLG)
This register provides S12CPMU status bits and flags.
0x0037
7
6
5
4
3
2
1
0
R
W
LOCK
UPOSC
RTIF
PORF
LVRF
LOCKIF
ILAF
OSCIF
Reset
0
Note 1
Note 2
0
0
Note 3
0
0
1. PORF is set to 1 when a power on reset occurs. Unaffected by System Reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by System Reset. Set by power on reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by System Reset. Cleared by power on reset.
= Unimplemented or Reserved
Figure 7-7. S12CPMU Flags Register (CPMUFLG)
Read: Anytime
S12P-Family Reference Manual, Rev. 1.13
208
Freescale Semiconductor
FREESCALE [ Freescale ]
