S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2.2
S12CPMU Reference Divider Register (CPMUREFDIV)
The CPMUREFDIV register provides a finer granularity for the PLL multiplier steps when using the
external oscillator as reference.
0x0035
7
6
5
4
3
2
1
0
R
W
0
0
REFFRQ[1:0]
REFDIV[3:0]
Reset
0
0
0
0
1
1
1
1
Figure 7-5. S12CPMU Reference Divider Register (CPMUREFDIV)
Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime.
Else write has no effect.
NOTE
Write to this register clears the LOCK and UPOSC status bits.
f
OSC
f
f
=
------------------------------------
If OSCLCP is enabled (OSCE=1)
If OSCLCP is disabled (OSCE=0)
REF
REF
(REFDIV + 1)
= f
IRC1M
The REFFRQ[1:0] bits are used to configure the internal PLL filter for optimal stability and lock time. For
correct PLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in Table 7-2.
If IRC1M is selected as REFCLK (OSCE=0) the PLL filter is fixed configured for the 1MHz <= f
2MHz range. The bits can still be written but will have no effect on the PLL filter configuration.
<=
REF
For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking
and/or insufficient stability).
Table 7-2. Reference Clock Frequency Selection if OSC_LCP is enabled
REFCLK Frequency Ranges
REFFRQ[1:0]
(OSCE=1)
1MHz <= fREF <= 2MHz
2MHz < fREF <= 6MHz
6MHz < fREF <= 12MHz
fREF >12MHz
00
01
10
11
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
207
FREESCALE [ Freescale ]
