S12 Clock, Reset and Power Management Unit (S12CPMU)
Write: Refer to each bit for individual write conditions
Table 7-3. CPMUFLG Field Descriptions
Field
Description
7
RTIF
Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing
a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request.
0 RTI time-out has not yet occurred.
1 RTI time-out has occurred.
6
Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing
PORF
a 1. Writing a 0 has no effect.
0 Power on reset has not occurred.
1 Power on reset has occurred.
5
Low Voltage Reset Flag — LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by
writing a 1. Writing a 0 has no effect.
LVRF
0 Low voltage reset has not occurred.
1 Low voltage reset has occurred.
4
PLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect.If enabled (LOCKIE=1), LOCKIF causes an interrupt request.
0 No change in LOCK bit.
LOCKIF
1 LOCK bit has changed.
3
Lock Status Bit — LOCK reflects the current state of PLL lock condition. Writes have no effect. While PLL is
unlocked (LOCK=0) fPLL is fVCO / 4 to protect the system from high core clock frequencies during the PLL
stabilization time tlock.
LOCK
0 VCOCLK is not within the desired tolerance of the target frequency.
f
PLL = fVCO/4.
1 VCOCLK is within the desired tolerance of the target frequency.
PLL = fVCO/(POSTDIV+1).
f
2
ILAF
Illegal Address Reset Flag — ILAF is set to 1 when an illegal address reset occurs. Refer to MMC chapter for
details. This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Illegal address reset has not occurred.
1 Illegal address reset has occurred.
1
Oscillator Interrupt Flag — OSCIF is set to 1 when UPOSC status bit changes. This flag can only be cleared
by writing a 1. Writing a 0 has no effect.If enabled (OSCIE=1), OSCIF causes an interrupt request.
0 No change in UPOSC bit.
OSCIF
1 UPOSC bit has changed.
0
Oscillator Status Bit — UPOSC reflects the status of the oscillator. Writes have no effect. While UPOSC=0 the
OSCCLK going to the MSCAN module is off. Entering Full Stop Mode UPOSC is cleared.
0 The oscillator is off or oscillation is not qualified by the PLL.
UPOSC
1 The oscillator is qualified by the PLL.
NOTE
The adaptive spike filter uses the VCO clock as a reference to continuously
qualify the external oscillator clock. Because of this, the PLL is always active
and a valid PLL configuration is required for the system to work properly.
Furthermore, the adaptive spike filter is used to determine the status of the
external oscillator (reflected in the UPOSC bit). Since this function also relies on
the VCO clock, loosing PLL lock status (LOCK=0, except for entering Pseudo
Stop Mode) means loosing the oscillator status information as well (UPOSC=0).
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
209
FREESCALE [ Freescale ]
