S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2.7
S12CPMU PLL Control Register (CPMUPLL)
This register controls the PLL functionality.
0x003A
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
0
FM1
FM0
Reset
0
0
0
0
0
0
0
0
Figure 7-10. S12CPMU PLL Control Register (CPMUPLL)
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has
no effect.
NOTE
Write to this register clears the LOCK and UPOSC status bits.
NOTE
Care should be taken to ensure that the bus frequency does not exceed the
specified maximum when frequency modulation is enabled.
NOTE
The frequency modulation (FM1 and FM0) can not be used if the Oscillator
Filter is enabled.
Table 7-6. CPMUPLL Field Descriptions
Field
Description
5, 4
PLL Frequency Modulation Enable Bits — FM1 and FM0 enable frequency modulation on the VCOCLK. This
FM1, FM0 is to reduce noise emission. The modulation frequency is fref divided by 16. See Table 7-7 for coding.
Table 7-7. FM Amplitude selection
FM Amplitude /
FM1
FM0
f
VCO Variation
0
0
1
1
0
1
0
1
FM off
1%
2%
4%
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
213
FREESCALE [ Freescale ]
