S12 Clock, Reset and Power Management Unit (S12CPMU)
Addres
s
Name
Bit 7
6
5
4
3
2
1
Bit 0
R
W
R
0
0
0x02F3 CPMUAPITR
0x02F4 CPMUAPIRH
0x02F5 CPMUAPIRL
APITR5
APITR4
APITR3
APITR2
APITR1
APITR0
APIR15
APIR14
APIR13
APIR12
APIR11
APIR10
APIR9
APIR8
W
R
APIR7
0
APIR6
0
APIR5
0
APIR4
0
APIR3
0
APIR2
0
APIR1
0
APIR0
0
W
R
RESERVED
0x02F6
CPMUTEST3
W
R
0
0
0
0x02F7 CPMUHTTR
HTOE
HTTR3
0
HTTR2
0
HTTR1
HTTR0
W
R
CPMU
0x02F8
TCTRIM[3:0]
IRCTRIM[9:8]
IRCTRIMH
W
R
CPMU
0x02F9
IRCTRIM[7:0]
IRCTRIML
W
R
0
0
0
0x02FA CPMUOSC
0x02FB CPMUPROT
OSCE
0
OSCBW
0
OSCFILT[4:0]
0
W
R
0
0
0
0
0
0
PROT
0
W
R
0
0
0
RESERVED
0x02FC
CPMUTEST2
W
= Unimplemented or Reserved
Figure 7-3. CPMU Register Summary
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
205
FREESCALE [ Freescale ]
