S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3
Memory Map and Registers
This section provides a detailed description of all registers accessible in the S12CPMU.
7.3.1
Module Memory Map
The S12CPMU registers are shown in Figure 7-3.
Addres
Name
Bit 7
6
5
4
3
2
1
Bit 0
s
R
W
R
CPMU
SYNR
0x0034
VCOFRQ[1:0]
REFFRQ[1:0]
SYNDIV[5:0]
0
0
0
CPMU
REFDIV
0x0035
0x0036
REFDIV[3:0]
W
R
0
0
CPMU
POSTDIV
POSTDIV[4:0]
W
R
LOCK
0
UPOSC
0
0x0037 CPMUFLG
0x0038 CPMUINT
0x0039 CPMUCLKS
0x003A CPMUPLL
0x003B CPMURTI
0x003C CPMUCOP
RTIF
RTIE
PORF
0
LVRF
0
LOCKIF
ILAF
0
OSCIF
OSCIE
W
R
LOCKIE
0
W
R
0
RTI
OSCSEL
COP
OSCSEL
PLLSEL
0
PSTP
0
PRE
0
PCE
0
W
R
0
0
FM1
FM0
W
R
RTDEC
RTR6
RTR5
RTR4
0
RTR3
0
RTR2
RTR1
RTR0
W
R
0
WCOP
0
RSBCK
0
CR2
0
CR1
0
CR0
0
W
R
WRTMASK
0
0
0
0
0
RESERVED
0x003D
CPMUTEST0
W
R
0
0
0
0
0
0
RESERVED
0x003E
CPMUTEST1
W
R
0
Bit 7
0
0
Bit 6
0
0
0
Bit 4
0
0
0
0
0
CPMU
0x003F
ARMCOP
W
R
Bit 5
Bit 3
Bit 2
HTDS
Bit 1
Bit 0
CPMU
0x02F0
VSEL
0
HTE
0
HTIE
LVIE
APIE
HTIF
LVIF
APIF
HTCTL
W
R
0
0
0
0
LVDS
CPMU
0x02F1
LVCTL
W
R
0
CPMU
0x02F2
APICLK
APIES
APIEA
APIFE
APICTL
W
= Unimplemented or Reserved
Figure 7-3. CPMU Register Summary
S12P-Family Reference Manual, Rev. 1.13
204
Freescale Semiconductor
FREESCALE [ Freescale ]
