S12 Clock, Reset and Power Management Unit (S12CPMU)
Figure 7-1. Block diagram of S12CPMU
Figure 7-2 shows a block diagram of the OSCLCP.
OSCCLK
Peak
Detector
Gain Control
VDDPLL = 1.8 V
VSSPLL
Rf
XTAL
EXTAL
Figure 7-2. OSCLCP Block Diagram
7.2
Signal Description
This section lists and describes the signals that connect off chip.
7.2.1
RESET
RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a known
start-up state. As an open-drain output it indicates that an MCU-internal reset has been triggered.
7.2.2
EXTAL and XTAL
These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is
the external clock input or the input to the crystal oscillator amplifier. XTAL is the output of the crystal
oscillator amplifier. The MCU internal OSCCLK is derived from the EXTAL input frequency. If OSCE=0,
S12P-Family Reference Manual, Rev. 1.13
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Freescale Semiconductor
FREESCALE [ Freescale ]
