S12 Clock, Reset and Power Management Unit (S12CPMU)
7.1.3
S12CPMU Block Diagram
Illegal Address Access
MMC
VDDR
VDD, VDDPLL, VDDF
(core supplies)
ILAF
VSSPLL
VSS
Low Voltage Detect VDDA
Low Voltage Interrupt
LVIE
LVDS
Low Voltage Detect VDDX
Voltage
VDDX
VSSX
VDDA
VSSA
RESET
LVRF
COP time out
S12CPMU
Regulator
3.13 to 5.5V
Power-On Detect
PORF
Power-On Reset
System Reset
Reset
monitor fail
Generator
Clock
Monitor
oscillator status Interrupt
OSCIE
UPOSC
UPOSC=0 sets PLLSEL bit
Loop
CAN_OSCCLK
(to MSCAN)
EXTAL
XTAL
OSCCLK
Controlled
Pierce
Oscillator
(OSCLCP)
4MHz-16MHz
adaptive
spike
filter
&
OSCFILT[4:0]
OSCBW
PLLSEL
REFDIV[3:0]
IRCTRIM[9:0]
POSTDIV[4:0]
ECLK2X
(Core Clock)
Internal
Reference
Clock
Reference
Divider
Post
Divider
1,2,..,32
PLLCLK
PSTP
divide
by 2
ECLK
(IRC1M)
divide
by 4
(Bus Clock)
IRCCLK
(to LCD)
OSCE
VCOFRQ[1:0]
divide
by 8
VCOCLK
BDM Clock
Phase
locked
REFCLK
FBCLK
Lock
detect
HT Interrupt
Loop with
internal
Filter (PLL)
HTDS
High
HTIE
Temperature
Sense
REFFRQ[1:0]
PLL Lock Interrupt
LOCK
LOCKIE
Periodic
Bus Clock
Divide by
Autonomous
2*(SYNDIV+1)
API_EXTCLK
ACLK
RC
Interrupt (API)
Osc.
SYNDIV[5:0]
API Interrupt
RTI Interrupt
APICLK
APIE
RTIE
UPOSC
UPOSC=0 clears
IRCCLK
IRCCLK
Real Time
Interrupt (RTI)
COP time out
to Reset
Generator
COP
Watchdog
COPCLK
RTICLK
OSCCLK
OSCCLK
COPOSCSEL
RTIOSCSEL
CPMUCOP
CPMURTI
PCE
PRE
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
201
FREESCALE [ Freescale ]
