Chapter 7
S12 Clock, Reset and Power Management Unit (S12CPMU)
Revision History
Version Revision Effective
Author
Description of Changes
Number
Date
Date
V01.00 16 Jan.07 16 Jan. 07
Initial release
V01.01
V01.02
9 July 08
7 Oct. 08
9 July 08
7 Oct. 08
added IRCLK to Block Diagram
clarified and detailed oscillator filter functionality
added note, that startup time of external oscillator tUPOSC must be
considered, especially when entering Pseudo Stop Mode
V01.03 11 Dec. 08 11 Dec. 08
V01.04 17 Jun. 09 17 Jun. 09
V01.05 27 Apr. 10 27 Apr. 10
Modified reset phase descriptions to reference fVCORST instead of
fPLLRST and correct typo of RESET pin sample point from 64 to 256
cycles in section: Description of Reset Operation
Major rework fixing typos, figures and tables and improved
description of Adaptive Oscillator Filter.
7.1
Introduction
This specification describes the function of the Clock, Reset and Power Management Unit (S12CPMU).
•
The Pierce oscillator (OSCLCP) provides a robust, low-noise and low-power external clock source.
It is designed for optimal start-up margin with typical crystal oscillators.
•
The Voltage regulator (IVREG) operates from the range 3.13V to 5.5V. It provides all the required
chip internal voltages and voltage monitors.
•
•
The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter.
The Internal Reference Clock (IRC1M) provides a1MHz clock.
7.1.1
Features
The Pierce Oscillator (OSCLCP) contains circuitry to dynamically control current gain in the output
amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity.
•
Supports crystals or resonators from 4MHz to 16MHz.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
197
FREESCALE [ Freescale ]
