S12 Clock, Reset and Power Management Unit (S12CPMU)
7.1.2
Modes of Operation
This subsection lists and briefly describes all operating modes supported by the S12CPMU.
7.1.2.1
Run Mode
The voltage regulator is in Full Performance Mode (FPM).
The Phase Locked Loop (PLL) is on.
The Internal Reference Clock (IRC1M) is on.
The API is available.
•
PLL Engaged Internal (PEI)
— This is the default mode after System Reset and Power-On Reset.
— The Bus Clock is based on the PLLCLK.
— After reset the PLL is configured for 64MHz VCOCLK operation
Post divider is 0x03, so PLLCLK is VCOCLK divided by 4, that is 16MHz and Bus Clock is
8MHz.
The PLL can be re-configured for other bus frequencies.
— The reference clock for the PLL (REFCLK) is based on internal reference clock IRC1M
PLL Engaged External (PEE)
•
•
— The Bus Clock is based on the PLLCLK.
— This mode can be entered from default mode PEI by performing the following steps:
– Configure the PLL for desired bus frequency.
– Program the reference divider (REFDIV[3:0] bits) to divide down oscillator frequency if
necessary.
– Enable the external oscillator (OSCE bit)
PLL Bypassed External (PBE)
— The Bus Clock is based on the Oscillator Clock (OSCCLK).
— This mode can be entered from default mode PEI by performing the following steps:
– Enable the external oscillator (OSCE bit)
– Wait for oscillator to start up (UPOSC=1)
– Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0).
— The PLLCLK is still on to filter possible spikes of the external oscillator clock.
7.1.2.2
Wait Mode
For S12CPMU Wait Mode is the same as Run Mode.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
199
FREESCALE [ Freescale ]
