S12 Clock, Reset and Power Management Unit (S12CPMU)
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High noise immunity due to input hysteresis and spike filtering.
Low RF emissions with peak-to-peak swing limited dynamically
Transconductance (gm) sized for optimum start-up margin for typical crystals
Dynamic gain control eliminates the need for external current limiting resistor
Integrated resistor eliminates the need for external bias resistor.
Low power consumption: Operates from internal 1.8V (nominal) supply, Amplitude control limits
power
The Voltage Regulator (IVREG) has the following features:
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Input voltage range from 3.13V to 5.5V
Low-voltage detect (LVD) with low-voltage interrupt (LVI)
Power-on reset (POR)
Low-voltage reset (LVR)
The Phase Locked Loop (PLL) has the following features:
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highly accurate and phase locked frequency multiplier
Configurable internal filter for best stability and lock time.
Frequency modulation for defined jitter and reduced emission
Automatic frequency lock detector
Interrupt request on entry or exit from locked condition
Reference clock either external (crystal) or internal square wave (1MHz IRC1M) based.
PLL stability is sufficient for LIN communication, even if using IRC1M as reference clock
The Internal Reference Clock (IRC1M) has the following features:
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Trimmable in frequency
Factory trimmed value for 1MHz in Flash Memory, can be overwritten by application if required
Other features of the S12CPMU include
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Clock monitor to detect loss of crystal
Autonomous periodical interrupt (API)
Bus Clock Generator
— Clock switch to select either PLLCLK or external crystal/resonator based Bus Clock
— PLLCLK divider to adjust system speed
System Reset generation from the following possible sources:
— Power-on reset (POR)
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— Low-voltage reset (LVR)
— Illegal address access
— COP time out
— Loss of oscillation (clock monitor fail)
— External pin RESET
S12P-Family Reference Manual, Rev. 1.13
198
Freescale Semiconductor
FREESCALE [ Freescale ]
