S12S Debug Module (S12SDBGV2)
6.1.4
Modes of Operation
The DBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU monitoring is disabled. When
the CPU enters active BDM Mode through a BACKGROUND command, the DBG module, if already
armed, remains armed.
The DBG module tracing is disabled if the MCU is secure, however, breakpoints can still be generated
Table 6-2. Mode Dependent Restriction Summary
BDM
Enable
BDM
Active
MCU
Secure
Comparator
Matches Enabled
Breakpoints
Possible
Tagging
Possible
Tracing
Possible
x
0
0
1
1
x
0
1
0
1
1
0
0
0
0
Yes
Yes
Yes
Yes
Yes
No
Only SWI
Yes
Active BDM not possible when not enabled
Yes
No
Yes
No
Yes
No
Yes
No
6.1.5
Block Diagram
TAGS
TAGHITS
BREAKPOINT REQUESTS
TO CPU
SECURE
CPU BUS
TRANSITION
MATCH0
COMPARATOR A
COMPARATOR B
COMPARATOR C
TAG &
MATCH
CONTROL
LOGIC
STATE
STATE SEQUENCER
MATCH1
MATCH2
STATE
TRACE
CONTROL
TRIGGER
TRACE BUFFER
READ TRACE DATA (DBG READ DATA BUS)
Figure 6-1. Debug Module Block Diagram
6.2
External Signal Description
There are no external signals associated with this module.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
157
FREESCALE [ Freescale ]
