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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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S12S Debug Module (S12SDBGV2)  
6.1.2  
Overview  
The comparators monitor the bus activity of the CPU module. A match can initiate a state sequencer  
transition. On a transition to the Final State, bus tracing is triggered and/or a breakpoint can be generated.  
Independent of comparator matches a transition to Final State with associated tracing and breakpoint can  
be triggered immediately by writing to the TRIG control bit.  
The trace buffer is visible through a 2-byte window in the register address map and can be read out using  
standard 16-bit word reads. Tracing is disabled when the MCU system is secured.  
6.1.3  
Features  
Three comparators (A, B and C)  
— Comparators A compares the full address bus and full 16-bit data bus  
— Comparator A features a data bus mask register  
— Comparators B and C compare the full address bus only  
— Each comparator features selection of read or write access cycles  
— Comparator B allows selection of byte or word access cycles  
— Comparator matches can initiate state sequencer transitions  
Three comparator modes  
— Simple address/data comparator match mode  
— Inside address range mode, Addmin Address Addmax  
— Outside address range match mode, Address < Addmin or Address > Addmax  
Two types of matches  
— Tagged — This matches just before a specific instruction begins execution  
— Force — This is valid on the first instruction boundary after a match occurs  
Two types of breakpoints  
— CPU breakpoint entering BDM on breakpoint (BDM)  
— CPU breakpoint executing SWI on breakpoint (SWI)  
Trigger mode independent of comparators  
— TRIG Immediate software trigger  
Four trace modes  
— Normal: change of flow (COF) PC information is stored (see 6.4.5.2.1) for change of flow  
definition.  
— Loop1: same as Normal but inhibits consecutive duplicate source address entries  
— Detail: address and data for all cycles except free cycles and opcode fetches are stored  
— Compressed Pure PC: all program counter addresses are stored  
4-stage state sequencer for trace buffer control  
— Tracing session trigger linked to Final State of state sequencer  
— Begin and End alignment of tracing to trigger  
S12P-Family Reference Manual, Rev. 1.13  
156  
Freescale Semiconductor  
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