S12S Debug Module (S12SDBGV2)
6.3
Memory Map and Registers
6.3.1
Module Memory Map
A summary of the registers associated with the DBG sub-block is shown in Figure 6-2. Detailed
descriptions of the registers and bits are given in the subsections that follow.
Address
Name
Bit 7
6
0
5
4
3
2
1
Bit 0
R
0
0
0x0020
DBGC1
ARM
BDM
DBGBRK
COMRV
W
TRIG
R
1TBF
0
0
0
0
0
0
0
SSF2
SSF1
0
SSF0
0x0021
0x0022
0x0023
0x0024
0x0025
0x0026
DBGSR
DBGTCR
DBGC2
W
R
TSOURCE
0
TRCMOD
TALIGN
W
R
0
0
0
0
0
ABCM
W
R
Bit 15
Bit 7
TBF
Bit 14
Bit 6
0
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
DBGTBH
DBGTBL
DBGCNT
W
R
W
1
R
CNT
W
R
W
R
0
0
0
0
0
0
0
0
0x0027 DBGSCRX
SC3
0
SC2
MC2
SC1
MC1
SC0
MC0
0x0027
0x0028
0x0028
0x0028
DBGMFR
W
2
3
4
R
W
R
DBGACTL
DBGBCTL
DBGCCTL
SZE
SZ
TAG
TAG
TAG
0
BRK
BRK
BRK
0
RW
RW
RW
0
RWE
RWE
RWE
0
NDB
0
COMPE
COMPE
COMPE
SZE
0
SZ
0
W
R
0
W
R
0
0
0x0029
0x002A
0x002B
0x002C
0x002D
DBGXAH
DBGXAM
DBGXAL
DBGADH
DBGADL
Bit 17
Bit 16
Bit 8
Bit 0
Bit 8
Bit 0
W
R
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
9
1
W
R
W
R
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
W
R
W
Figure 6-2. Quick Reference to DBG Registers
S12P-Family Reference Manual, Rev. 1.13
158
Freescale Semiconductor
FREESCALE [ Freescale ]
