Chapter 6
S12S Debug Module (S12SDBGV2)
Table 6-1. Revision History
Revision
Date
Sections
Affected
Revision Number
Summary of Changes
02.07
02.08
02.09
13.DEC.2007
09.MAY.2008
29.MAY.2008
6.5
Added application information
General
6.4.5.4
Spelling corrections. Revision history format changed.
Added note for end aligned, PurePC, rollover case.
6.1
Introduction
The S12SDBG module provides an on-chip trace buffer with flexible triggering capability to allow non-
intrusive debug of application software. The S12SDBG module is optimized for S12SCPU debugging.
Typically the S12SDBG module is used in conjunction with the S12SBDM module, whereby the user
configures the S12SDBG module for a debugging session over the BDM interface. Once configured the
S12SDBG module is armed and the device leaves BDM returning control to the user program, which is
then monitored by the S12SDBG module. Alternatively the S12SDBG module can be configured over a
serial interface using SWI routines.
6.1.1
Glossary Of Terms
COF: Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt.
BDM: Background Debug Mode
S12SBDM: Background Debug Module
DUG: Device User Guide, describing the features of the device into which the DBG is integrated.
WORD: 16 bit data entity
Data Line: 20 bit data entity
CPU: S12SCPU module
DBG: S12SDBG module
POR: Power On Reset
Tag: Tags can be attached to CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches
the execution stage a tag hit occurs.
S12P-Family Reference Manual, Rev. 1.13
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