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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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S12S Debug Module (S12SDBGV2)  
Read: Anytime  
Write: Never  
Table 6-5. DBGSR Field Descriptions  
Description  
Field  
7
TBF  
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was  
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF  
bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization.  
Other system generated resets have no affect on this bit  
This bit is also visible at DBGCNT[7]  
2–0  
SSF[2:0]  
State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During  
a debug session on each transition to a new state these bits are updated. If the debug session is ended by  
software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer  
before disarming. If a debug session is ended by an internal event, then the state sequencer returns to state0  
and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state  
sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 6-6.  
Table 6-6. SSF[2:0] — State Sequence Flag Bit Encoding  
SSF[2:0]  
000  
Current State  
State0 (disarmed)  
State1  
001  
010  
State2  
011  
State3  
100  
Final State  
Reserved  
101,110,111  
6.3.2.3  
Debug Trace Control Register (DBGTCR)  
Address: 0x0022  
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
TSOURCE  
TRCMOD  
TALIGN  
Reset  
0
0
0
0
0
0
0
Figure 6-5. Debug Trace Control Register (DBGTCR)  
Read: Anytime  
Write: Bit 6 only when DBG is neither secure nor armed.Bits 3,2,0 anytime the module is disarmed.  
Table 6-7. DBGTCR Field Descriptions  
Field  
Description  
6
Trace Source Control Bit — The TSOURCE bit enables a tracing session given a trigger condition. If the MCU  
TSOURCE system is secured, this bit cannot be set and tracing is inhibited.  
This bit must be set to read the trace buffer.  
0 Debug session without tracing requested  
1 Debug session with tracing requested  
S12P-Family Reference Manual, Rev. 1.13  
Freescale Semiconductor  
161  
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