S12S Debug Module (S12SDBGV2)
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
R
0x002E DBGADHM
Bit 15
14
13
12
11
10
9
Bit 8
W
R
0x002F DBGADLM
Bit 7
6
5
4
3
2
1
Bit 0
W
1
2
3
4
This bit is visible at DBGCNT[7] and DBGSR[7]
This represents the contents if the Comparator A control register is blended into this address.
This represents the contents if the Comparator B control register is blended into this address
This represents the contents if the Comparator C control register is blended into this address
Figure 6-2. Quick Reference to DBG Registers
6.3.2
Register Descriptions
This section consists of the DBG control and trace buffer register descriptions in address order. Each
comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F
in the DBG module register address map. When ARM is set in DBGC1, the only bits in the DBG module
registers that can be written are ARM, TRIG, and COMRV[1:0]
6.3.2.1
Debug Control Register 1 (DBGC1)
Address: 0x0020
7
6
5
4
3
2
1
0
R
W
0
0
0
ARM
0
BDM
DBGBRK
COMRV
TRIG
0
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-3. Debug Control Register (DBGC1)
Read: Anytime
Write: Bits 7, 1, 0 anytime
Bit 6 can be written anytime but always reads back as 0.
Bits 4:3 anytime DBG is not armed.
NOTE
When disarming the DBG by clearing ARM with software, the contents of
bits[4:3] are not affected by the write, since up until the write operation,
ARM = 1 preventing these bits from being written. These bits must be
cleared using a second write if required.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
159
FREESCALE [ Freescale ]
