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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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Background Debug Module (S12SBDMV1)  
5.4.9  
SYNC — Request Timed Reference Pulse  
The SYNC command is unlike other BDM commands because the host does not necessarily know the  
correct communication speed to use for BDM communications until after it has analyzed the response to  
the SYNC command. To issue a SYNC command, the host should perform the following steps:  
1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication  
frequency (The lowest serial communication frequency is determined by the settings for the VCO  
clock (CPMUSYNR). The BDM clock frequency is always VCO clock frequency divided by 8.)  
2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically  
one cycle of the host clock.)  
3. Remove all drive to the BKGD pin so it reverts to high impedance.  
4. Listen to the BKGD pin for the sync response pulse.  
Upon detecting the SYNC request from the host, the target performs the following steps:  
1. Discards any incomplete command received or bit retrieved.  
2. Waits for BKGD to return to a logic one.  
3. Delays 16 cycles to allow the host to stop driving the high speedup pulse.  
4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency.  
5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD.  
6. Removes all drive to the BKGD pin so it reverts to high impedance.  
The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed  
for subsequent BDM communications. Typically, the host can determine the correct communication speed  
within a few percent of the actual target speed and the communication protocol can easily tolerate speed  
errors of several percent.  
As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is  
discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication. After the  
SYNC response, the target will consider the next negative edge (issued by the host) as the start of a new  
BDM command or the start of new SYNC request.  
Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the  
same as in a regular SYNC command. Note that one of the possible causes for a command to not be  
acknowledged by the target is a host-target synchronization problem. In this case, the command may not  
have been understood by the target and so an ACK response pulse will not be issued.  
5.4.10 Instruction Tracing  
When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM  
firmware and executes a single instruction in the user code. Once this has occurred, the CPU is forced to  
return to the standard BDM firmware and the BDM is active and ready to receive a new command. If the  
TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or  
tracing through the user code one instruction at a time.  
S12P-Family Reference Manual, Rev. 1.13  
Freescale Semiconductor  
151  
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