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MC908MR32CFUE 参数 Datasheet PDF下载

MC908MR32CFUE图片预览
型号: MC908MR32CFUE
PDF下载: 下载PDF文件 查看货源
内容描述: [MC908MR32CFUE ]
分类和应用:
文件页数/大小: 308 页 / 4411 K
品牌: FREESCALE [ Freescale ]
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Clock Generator Module (CGM)  
For proper operation, the external filter capacitor must be chosen according to this  
equation:  
V
DDA  
--------------  
C
= C  
FACT  
F
f
RDV  
For acceptable values of CFACT, see 4.8 Acquisition/Lock Time Specifications.  
For the value of VDDA, choose the voltage potential at which the MCU is operating.  
If the power supply is variable, choose a value near the middle of the range of  
possible supply values.  
This equation does not always yield a commonly available capacitor size, so round  
to the nearest available size. If the value is between two different sizes, choose the  
higher value for better stability. Choosing the lower size may seem attractive for  
acquisition time improvement, but the PLL can become unstable. Also, always  
choose a capacitor with a tight tolerance (±20 percent or better) and low  
dissipation.  
4.8.4 Reaction Time Calculation  
The actual acquisition and lock times can be calculated using the equations here.  
These equations yield nominal values under these conditions:  
Correct selection of filter capacitor, CF, see 4.8.3 Choosing a Filter  
Capacitor  
Room temperature operation  
Negligible external leakage on CGMXFC  
Negligible noise  
The K factor in the equations is derived from internal PLL parameters. KACQ is the  
K factor when the PLL is configured in acquisition mode, and KTRK is the K factor  
when the PLL is configured in tracking mode. See 4.3.2.2 Acquisition and  
Tracking Modes.  
V
8
DDA  
-------------- --------------  
t
=
ACQ  
f
K
RDV  
ACQ  
V
4
DDA  
-------------- -------------  
t
=
AL  
f
K
RDV  
TRK  
t
= t  
+ t  
ACQ AL  
Lock  
NOTE:  
The inverse proportionality between the lock time and the reference frequency.  
In automatic bandwidth control mode, the acquisition and lock times are quantized  
into units based on the reference frequency. See 4.3.2.3 Manual and Automatic  
PLL Bandwidth Modes A certain number of clock cycles, nACQ, is required to  
ascertain that the PLL is within the tracking mode entry tolerance, TRK, before  
Data Sheet  
76  
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0  
Clock Generator Module (CGM)  
MOTOROLA  
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