Clock Generator Module (CGM)
4.8 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the most
critical PLL design parameters. Proper design and use of the PLL ensures the
highest stability and lowest acquisition/lock times.
4.8.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the reaction
time, within specified tolerances, of the system to a step input. In a PLL, the step
input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance
is usually specified as a percent of the step input or when the output settles to the
desired value plus or minus a percent of the frequency change. Therefore, the
reaction time is constant in this definition, regardless of the size of the step input.
For example, consider a system with a 5 percent acquisition time tolerance. If a
command instructs the system to change from 0 Hz to 1 MHz, the acquisition time
is the time taken for the frequency to reach 1 MHz ± 50 kHz. Fifty kHz = 5% of the
1-MHz step input. If the system is operating at 1 MHz and suffers a –100-kHz noise
hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz ±5 kHz.
Five kHz = 5% of the 100-kHz step input.
Other systems refer to acquisition and lock times as the time the system takes to
reduce the error between the actual output and the desired output to within
specified tolerances. Therefore, the acquisition or lock time varies according to the
original error in the output. Minor errors may not even be registered. Typical PLL
applications prefer to use this definition because the system requires the output
frequency to be within a certain tolerance of the desired frequency regardless of
the size of the initial error.
The discrepancy in these definitions makes it difficult to specify an acquisition or
lock time for a typical PLL. Therefore, the definitions for acquisition and lock times
for this module are:
•
Acquisition time, tACQ, is the time the PLL takes to reduce the error between
the actual output frequency and the desired output frequency to less than
the tracking mode entry tolerance, ∆TRK. Acquisition time is based on an
initial frequency error,
(fDES – fORIG)/fDES, of not more than ±100 percent. In automatic bandwidth
control mode (see 4.3.2.3 Manual and Automatic PLL Bandwidth
Modes), acquisition time expires when the ACQ bit becomes set in the PLL
bandwidth control register (PBWC).
•
Lock time, tLock, is the time the PLL takes to reduce the error between the
actual output frequency and the desired output frequency to less than the
lock mode entry tolerance, ∆Lock. Lock time is based on an initial frequency
error, (fDES – fORIG)/fDES, of not more than ±100 percent. In automatic
bandwidth control mode, lock time expires when the LOCK bit becomes set
in the PLL bandwidth control register (PBWC). See 4.3.2.3 Manual and
Automatic PLL Bandwidth Modes.
Data Sheet
74
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
Clock Generator Module (CGM)
MOTOROLA
FREESCALE [ Freescale ]
