Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
exiting acquisition mode. A certain number of clock cycles, nTRK, is required to
ascertain that the PLL is within the lock mode entry tolerance, ∆Lock. Therefore, the
acquisition time, tACQ, is an integer multiple of nACQ RDV
/f
, and the acquisition to
lock time, tAL, is an integer multiple of nTRK/fRDV. Also, since the average frequency
over the entire measurement period must be within the specified tolerance, the
total time usually is longer than tLock as calculated in the previous example.
In manual mode, it is usually necessary to wait considerably longer than tLock
before selecting the PLL clock (see 4.3.3 Base Clock Selector Circuit) because
the factors described in 4.8.2 Parametric Influences on Reaction Time may slow
the lock time considerably.
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA Clock Generator Module (CGM)
Data Sheet
77
FREESCALE [ Freescale ]
