Memory
Memory Map
Addr.
$005E
$005F
Register Name
Bit 7
MUL7
0
6
MUL6
1
5
MUL5
1
4
MUL4
0
3
VRS7
0
2
VRS6
1
1
Bit 0
VRS4
0
Read:
PLL Programming Register
VRS5
1
(PPG) Write:
See page 72.
Reset:
Unimplemented
Read:
SIM Break Status Register
R
R
R
R
R
R
BW
R
$FE00
$FE01
$FE03
(SBSR) Write:
See page 207.
Reset:
Read: POR
0
LVI
R
PIN
R
COP
R
ILOP
ILAD
R
MENRST
0
R
0
SIM Reset Status Register
See page 207.
(SRSR) Write:
R
1
R
0
R
0
Reset:
Read:
0
0
0
0
SIM Break Flag Control
BCFE
R
R
R
R
R
R
R
Register (SBFCR) Write:
See page 208.
Reset:
0
0
FLASH Control Register Read:
(FLCR)
0
0
0
0
0
0
HVEN
0
MASS
0
ERASE
0
PGM
0
Write:
$FE08
See page 41.
Reset:
0
Read:
Break Address Register High
Bit 15
0
14
13
0
12
0
11
0
10
0
9
0
1
Bit 8
0
$FE0C
$FE0D
$FE0E
$FE0F
$FF7E
(BRKH) Write:
See page 276.
Reset:
0
Read:
Break Address Register Low
Bit 7
0
6
0
5
4
3
2
Bit 0
(BRKL) Write:
See page 276.
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Break Status and Control
Register (BRKSCR) Write:
BRKE
BRKA
See page 276.
Reset:
0
0
0
0
TRPSEL
0
0
0
0
0
0
0
0
0
0
0
Read: LVIOUT
LVI Status and Control Register
See page 109.
(LVISCR) Write:
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Reset:
Read:
FLASH Block Protect Register
BPR7
0
BPR6
0
BPR5
0
BPR4
0
BPR3
0
BPR2
0
BPR1
0
BPR0
0
(FLBPR) Write:
See page 45.
Reset:
Read:
Low byte of reset vector
Clear COP counter
Unaffected by reset
COP Control Register
$FFFF
(COPCTL) Write:
See page 85.
Reset:
U = Unaffected X = Indeterminate
R
= Reserved
Bold
= Buffered
= Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 8 of 8)
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA
Data Sheet
37
Memory
FREESCALE [ Freescale ]
