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MC908MR32CFUE 参数 Datasheet PDF下载

MC908MR32CFUE图片预览
型号: MC908MR32CFUE
PDF下载: 下载PDF文件 查看货源
内容描述: [MC908MR32CFUE ]
分类和应用:
文件页数/大小: 308 页 / 4411 K
品牌: FREESCALE [ Freescale ]
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Memory  
Addr.  
Register Name  
Bit 7  
6
Bit 14  
R
5
Bit 13  
R
4
Bit 12  
R
3
Bit 11  
R
2
Bit 10  
R
1
Bit 9  
R
Bit 0  
Bit 8  
R
Read: Bit 15  
TIMB Counter Register High  
$0052  
(TBCNTH) Write:  
R
0
See page 267.  
TIMB Counter Register Low  
See page 267.  
Reset:  
0
0
0
0
0
0
0
Read: Bit 7  
Bit 6  
R
Bit 5  
R
Bit 4  
R
Bit 3  
R
Bit 2  
R
Bit 1  
R
Bit 0  
R
$0053  
$0054  
$0055  
$0056  
$0057  
$0058  
$0059  
$005A  
$005B  
$005C  
$005D  
(TBCNTL) Write:  
R
0
Reset:  
Read:  
0
0
0
0
0
0
0
TIMB Counter Modulo Register  
Bit 15  
1
Bit 14  
1
Bit 13  
1
Bit 12  
1
Bit 11  
1
Bit 10  
1
Bit 9  
1
Bit 8  
1
High (TBMODH) Write:  
See page 268.  
Reset:  
Read:  
TIMB Counter Modulo Register  
Bit 7  
Bit 6  
1
Bit 5  
1
Bit 4  
1
Bit 3  
1
Bit 2  
1
Bit 1  
1
Bit 0  
1
Low (TBMODL) Write:  
See page 268.  
Reset:  
1
Read: CH0F  
TIMB Channel 0 Status/Control  
See page 269.  
CH0IE  
0
MS0B  
0
MS0A  
0
ELS0B  
0
ELS0A  
0
TOV0 CH0MAX  
Register (TBSC0) Write:  
0
0
Reset:  
Read:  
0
0
TIMB Channel 0 Register High  
Bit 15  
Bit 14  
Bit 13  
Bit 12  
Bit 11  
Bit 10  
Bit 9  
Bit 8  
(TBCH0H) Write:  
See page 272.  
Reset:  
Read:  
Indeterminate after reset  
Bit 4 Bit 3  
Indeterminate after reset  
TIMB Channel 0 Register Low  
Bit 7  
Bit 6  
Bit 5  
Bit 2  
Bit 1  
Bit 0  
(TBCH0L) Write:  
See page 272.  
Reset:  
Read: CH1F  
0
R
0
TIMB Channel 1 Status/Control  
See page 269.  
CH1IE  
0
MS1A  
0
ELS1B  
0
ELS1A  
0
TOV1 CH1MAX  
Register (TBSC1) Write:  
0
0
Reset:  
Read:  
0
0
TIMB Channel 1 Register High  
Bit 15  
Bit 14  
Bit 13  
Bit 12  
Bit 11  
Bit 10  
Bit 9  
Bit 8  
(TBCH1H) Write:  
See page 272.  
Reset:  
Read:  
Indeterminate after reset  
Bit 4 Bit 3  
TIMB Channel 1 Register Low  
Bit 7  
Bit 6  
Bit 5  
Bit 2  
Bit 1  
Bit 0  
(TBCH1L) Write:  
See page 272.  
Reset:  
Read:  
Indeterminate after reset  
PLLF  
1
1
R
1
1
R
1
1
R
1
PLL Control Register  
PLLIE  
0
PLLON  
BCS  
(PCTL) Write:  
R
R
See page 69.  
Reset:  
Read:  
0
1
ACQ  
0
0
1
LOCK  
0
0
0
0
PLL Bandwidth Control  
AUTO  
XLD  
Register (PBWC) Write:  
See page 71.  
Reset:  
R
R
0
R
0
R
0
R
0
0
0
0
U = Unaffected X = Indeterminate  
R
= Reserved  
Bold  
= Buffered  
= Unimplemented  
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 7 of 8)  
Data Sheet  
36  
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0  
MOTOROLA  
Memory  
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