Memory
Memory Map
Addr.
Register Name
Bit 7
R7
6
5
4
3
2
1
Bit 0
R0
Read:
(SCDR) Write:
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
SCI Data Register
$003D
T7
T0
See page 192.
Reset:
Read:
Unaffected by reset
0
R
0
0
R
0
0
SCI Baud Rate Register
SCP1
SCP0
R
SCR2
SCR1
0
SCR0
0
$003E
$003F
$0040
$0041
$0042
$0043
$0044
$0045
$0046
(SCBR) Write:
See page 192.
Reset:
Read:
0
0
0
0
0
0
0
0
0
IRQF
IRQ Status/Control Register
IMASK1 MODE1
(ISCR) Write:
See page 105.
R
0
R
0
R
0
R
0
ACK1
0
Reset:
0
0
0
Read: COCO
ADC Status and Control
Register (ADSCR) Write:
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1 ADCH0
R
0
See page 54.
Reset:
0
0
0
0
1
0
1
0
1
0
1
AD9
R
1
AD8
R
Read:
0
ADC Data Register High
Right Justified Mode (ADRH) Write:
R
R
R
R
R
R
See page 56.
Reset:
Unaffected by reset
Read: AD7
AD6
R
AD5
R
AD4
R
AD3
R
AD2
R
AD1
R
AD0
R
ADC Data Register Low
Right Justified Mode (ADRL) Write:
R
See page 56.
Reset:
Unaffected by reset
Read:
0
R
0
ADC Clock Register
ADIV2
ADIV1
ADIV0
0
ADICLK
0
MODE1
0
MODE0
1
0
0
(ADCLK) Write:
See page 57.
Reset:
0
SPRIE
0
0
Read:
SPI Control Register
R
0
SPMSTR
CPOL
CPHA
SPWOM
0
SPE
0
SPTIE
0
(SPCR) Write:
See page 228.
Reset:
1
OVRF
R
0
MODF
R
1
SPTE
R
Read: SPRF
SPI Status and Control
Register (SPSCR) Write:
ERRIE
MODFEN
SPR1
SPR0
R
0
See page 229.
Reset:
0
0
0
1
0
0
0
Read:
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SPI Data Register
(SPDR) Write:
See page 232.
Reset:
Unaffected by reset
$0047
↓
$0050
Unimplemented
Read: TOF
0
0
TIMB Status/Control Register
See page 265.
TOIE
TSTOP
1
PS2
0
PS1
0
PS0
0
$0051
(TBSC) Write:
0
0
TRST
0
R
0
Reset:
0
U = Unaffected X = Indeterminate
R
= Reserved
Bold
= Buffered
= Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 6 of 8)
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA
Data Sheet
35
Memory
FREESCALE [ Freescale ]
